Making a VGA Driver in SystemVerilog lukaswerner.com

Lukas Werner describes building a VGA driver in SystemVerilog for a DE10-Lite FPGA, using a divided 50 MHz clock and horizontal and vertical counters to generate 640×480 display timing. He then loaded an Asterix image into ROM and added alpha transparency, comparing simple masking, a bit-shift approximation, and multiplication-based compositing.