Nvidia Vera’s System Architecture: Pushing Bandwidth chipsandcheese.com

Chester Lam reports that Nvidia’s Vera server chip combines a 164 MB shared L3 cache with a 1024-bit LPDDR5X interface delivering up to 1.228 TB/s, while keeping local memory latency under 200 ns even under heavy load. Benchmarks show strong per-core performance and advantages in memory-bandwidth-heavy workloads, but weaker throughput than higher-core-count Graviton 5 in many tests and high cross-socket latency.