prjcombine codeberg.org

Project Combine is a Rust-based effort to reverse-engineer FPGA and CPLD device geometry, interconnects, bitstreams and timing, and publish the results as databases and documentation. Its coverage includes SiliconBlue, Xilinx and several Lattice families; geometry is complete for many targets, while full databases and testing are complete for Xilinx XC9500 and CoolRunner XPLA3 devices.